M. Koushik, Shashidhar Shivanagi, Gaurav Gupta, J. Qumar, D. Saravanan
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Implementation of G.723.1Decoder on Zynq FPGA using HLS
For the speech communication techniques there is a lot of scope nowadays. Due to number of applications increasing, there is a need for the approach for the data compression techniques which uses bandwidth and storage space. In this MP-MLQ excitation which has high rate working mode ITU-T G723.1 algorithm is implemented. The G723.1 Decoder is implemented through HLS on to the Zynq-7 ZC706 FPGA Evaluation Board. The comparison of the area utilization is done at C-synthesis level, post-synthesis level, post-implementation level.
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