0.18μm CMOS带隙基准的CS-VCO设计

V. G. Nasre, G. Asutkar
{"title":"0.18μm CMOS带隙基准的CS-VCO设计","authors":"V. G. Nasre, G. Asutkar","doi":"10.1109/RTEICT.2017.8256621","DOIUrl":null,"url":null,"abstract":"Presently design of a linear and wide range voltage controlled oscillator for analog and mixed mode signal applications with lesser design cycle time is a challenging work for Electronics Engineers. Band Gap reference voltage source is required, since the power supply noise is one of the important factors that affect the PLL noise performance. This paper describes the new design technique of the Band Gap Reference Current Starved Voltage Controlled Oscillator (BG-CSVCO) circuit to reduce power supply noise for PLL application. The BG-CSVCO circuit is designed and simulated using 0.18μm CMOS Technology. The BG-CSVCO has frequency range from 1.59 MHz to 2.87 GHz for the tuning range 0.2V to 1.8V and power consumption is 1.336mW. The supply voltage VDD is 1.8V.","PeriodicalId":342831,"journal":{"name":"2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":"227 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Design of CS-VCO with band gap reference in 0.18μm CMOS technology\",\"authors\":\"V. G. Nasre, G. Asutkar\",\"doi\":\"10.1109/RTEICT.2017.8256621\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Presently design of a linear and wide range voltage controlled oscillator for analog and mixed mode signal applications with lesser design cycle time is a challenging work for Electronics Engineers. Band Gap reference voltage source is required, since the power supply noise is one of the important factors that affect the PLL noise performance. This paper describes the new design technique of the Band Gap Reference Current Starved Voltage Controlled Oscillator (BG-CSVCO) circuit to reduce power supply noise for PLL application. The BG-CSVCO circuit is designed and simulated using 0.18μm CMOS Technology. The BG-CSVCO has frequency range from 1.59 MHz to 2.87 GHz for the tuning range 0.2V to 1.8V and power consumption is 1.336mW. The supply voltage VDD is 1.8V.\",\"PeriodicalId\":342831,\"journal\":{\"name\":\"2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)\",\"volume\":\"227 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RTEICT.2017.8256621\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RTEICT.2017.8256621","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

摘要

目前,为模拟和混合模式信号应用设计一种具有较短设计周期的线性宽范围压控振荡器对电子工程师来说是一项具有挑战性的工作。需要带隙参考电压源,因为电源噪声是影响锁相环噪声性能的重要因素之一。本文介绍了带隙基准缺流压控振荡器(BG-CSVCO)电路的新设计技术,以降低锁相环应用中的电源噪声。采用0.18μm CMOS工艺设计并仿真了BG-CSVCO电路。BG-CSVCO的频率范围为1.59 MHz ~ 2.87 GHz,调谐范围为0.2V ~ 1.8V,功耗为1.336mW。电源电压VDD为1.8V。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design of CS-VCO with band gap reference in 0.18μm CMOS technology
Presently design of a linear and wide range voltage controlled oscillator for analog and mixed mode signal applications with lesser design cycle time is a challenging work for Electronics Engineers. Band Gap reference voltage source is required, since the power supply noise is one of the important factors that affect the PLL noise performance. This paper describes the new design technique of the Band Gap Reference Current Starved Voltage Controlled Oscillator (BG-CSVCO) circuit to reduce power supply noise for PLL application. The BG-CSVCO circuit is designed and simulated using 0.18μm CMOS Technology. The BG-CSVCO has frequency range from 1.59 MHz to 2.87 GHz for the tuning range 0.2V to 1.8V and power consumption is 1.336mW. The supply voltage VDD is 1.8V.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信