{"title":"快速实现DSP算法的算法评估:一个抽取滤波器的例子","authors":"P. Israsena, S. Wongnamkum","doi":"10.1109/ICALIP.2008.4590131","DOIUrl":null,"url":null,"abstract":"This paper discuses a design flow that integrates the developments of DSP algorithms and FPGA hardware to increase performance and reduce development time. A decimation filter for analog-to-digital conversion is implemented as an example, with the results analyzed and compared to the more conventional RTL coding and synthesis approach.","PeriodicalId":175885,"journal":{"name":"2008 International Conference on Audio, Language and Image Processing","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Rapid implementation of DSP algorithms for algorithm evaluation: a decimation filter example\",\"authors\":\"P. Israsena, S. Wongnamkum\",\"doi\":\"10.1109/ICALIP.2008.4590131\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper discuses a design flow that integrates the developments of DSP algorithms and FPGA hardware to increase performance and reduce development time. A decimation filter for analog-to-digital conversion is implemented as an example, with the results analyzed and compared to the more conventional RTL coding and synthesis approach.\",\"PeriodicalId\":175885,\"journal\":{\"name\":\"2008 International Conference on Audio, Language and Image Processing\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-07-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 International Conference on Audio, Language and Image Processing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICALIP.2008.4590131\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 International Conference on Audio, Language and Image Processing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICALIP.2008.4590131","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Rapid implementation of DSP algorithms for algorithm evaluation: a decimation filter example
This paper discuses a design flow that integrates the developments of DSP algorithms and FPGA hardware to increase performance and reduce development time. A decimation filter for analog-to-digital conversion is implemented as an example, with the results analyzed and compared to the more conventional RTL coding and synthesis approach.
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