An accurate power and temperature simulation framework for Network-on-Chip

With the CMOS technology node decreasing rapidly, many homogeneous and heterogeneous cores are enabled to be integrated onto a single chip in order to improve the performance of chips. However, due to the aggressive technology scaling, following the improvement of system integration, the rise of power density increases rapidly, which causes a significant number of hot spots and poses an enormous threat to the performance and lifetime of chips. For better modulation of this problem, an accurate temperature simulation platform is urgently necessary. In this paper, based on the open-source Gem5, McPAT and Hotspot simulators, a novel simulation framework is built for accurate power and temperature simulation of Network-on-Chips. Gem5 is adopted to simulate the specified CPU model and obtained access statistics. McPAT and Hotspot are utilized to estimate the power and temperature of the corresponding architecture, respectively. Afterwards, a set of temperature-aware dynamic task scheduling algorithms are then conducted to evaluate the performance of the proposed simulation framework.