Designing D Flip-Flop using a 3×3 reversible gate

Due to the increasing need for miniaturization and power consumption reduction, reversible gates were provided in which, the number of inputs and outputs are equal and the power consumption is zero. In this paper, D flip-flop has been designed using 3×3 retrievable gateways and all of the proposed circuits have been evaluated in terms of cost metrics. In this paper, the reversible gates were finally combined to reduce the delay (the number of gates) in the D flip flop circuit. Here, the Function was used in Simulink and Matlab software, and reversible gates were designed and provided with a D flip-flop.