A generic and efficient modeling of phase margin of high performance CMOS OpAmps

This paper presents an efficient approach to model Phase Margin (PM) of high performance amplifiers. In this approach, effects of higher order poles and zeros are modeled into an equivalent secondary pole, referred as Effective Second Pole (ESP). The notion of ESP is very useful, particularly, for designing a high bandwidth amplifier where a number of parasitic poles and zeros simultaneously influence the phase margin. Moreover, a model of the ESP can be developed empirically without tracking the relative positions of poles and zeros across different corners of the design of experiments. Effectiveness of the empirically modeled ESP has been demonstrated by sizing two high performance CMOS amplifiers and comparing the predicted results (using the proposed models) to those obtained from transistor level simulations using SPICE.