65纳米CMOS工艺d波段比3注入锁定分频器的评价

2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) Pub Date : 2015-08-01 DOI:10.1109/RFIT.2015.7377928

Yen-Liang Yeh, Yu-Cheng Liu, Hong-Yeh Chang, Kevin Chen

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引用次数: 3

摘要

本文提出了一种采用65 CMOS工艺的d波段分频器。采用二次谐波增强技术，可以在毫米波频段内提高输入灵敏度和锁定范围，而无需增加直流功耗。由于输入频率为134.6 GHz，射频功率为-8.5 dBm，在无变容调谐的情况下，测量的锁定范围为0.4 GHz，输出功率高于-18 dBm。核心直流功耗为2.3 mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Evaluation of a D-band divide-by-3 injection-locked frequency divider in 65 nm CMOS process

In this paper, a D-band divider-by-3 injection-locked frequency divider is presented using 65 CMOS process. By using the technique of the second harmonic boosting, the input sensitivity and locking range can be enhanced in the millimeter-wave band without additional dc power consumption. As the input frequency is 134.6 GHz with a RF power of -8.5 dBm, the measured locking range is 0.4 GHz without varactor tuning, and the output power is high than -18 dBm. The core dc power consumption is 2.3 mW.

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来源期刊

2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)

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