J. Cheah, E. Kwek, E. Low, C. Quek, C. Yong, R. Enright, J. Hirbawi, A. Lee, Hongyu Xie, Long Wei, L. Luong, Jianping Pan, Shih-Tsung Yang, Walter Lau, Wai-Lim Ngai
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Design of a low-cost integrated 0.25 /spl mu/m CMOS Bluetooth SOC in 16.5 mm/sup 2/ silicon area
A complete 0.25 /spl mu/m CMOS SOC Bluetooth solution adopts a two-die in a single MCM chip packaging approach with minimum product cost as the most important design goal while maintaining competitive power consumption and RF performance.