Design and Implementation of a Data Stream Anonymization Core on FPGA

Data privacy has become the center of attention to many researchers and engineers. With high speed data transmission, data privacy can be at risk. Data stream anonymization is a fairly new and effective technique that is being currently investigated. It aims to protect data from third-party attackers. A user must keep in mind that when applying anonymization on a dataset, there will be a tradeoff between data utility and the risk of data identification. I n this paper, w e propose various anonymization cores that can be used to hide the sensitive parts of the data. The hardware implementation on FPGA of these cores is also discussed. Each implementation takes into consideration the trade-off between the throughput and the power consumption in addition to the application type and specifications. The first architecture treats a simple application where two anonymization techniques are used (i.e. Perturbation and character masking). The second implementation requires more complex anonymization techniques and extends K-anonymity criteria and L-diversity for more sensitive applications where data identification is crucial. Results are compared with existing work implementations and many improvements are applied in terms of resource utilization and throughput.