{"title":"提高路由器/服务器组合的性能","authors":"Voravit Tanyingyong, M. Hidell, Peter Sjödin","doi":"10.1109/HPSR.2012.6260827","DOIUrl":null,"url":null,"abstract":"A modern PC-based router can provide as competitive service as a specialized hardware router while offering more flexibility and possibility to extend beyond routing. We focus on a use case in which the PC-based router also functions as a server. In this paper, we propose a multi-core based architecture for a combined router/server that efficiently provides simultaneous packet forwarding and server processing. We improve the overall performance by creating a fast path for packet forwarding through caching flow entries in on-board classification hardware on the NIC. We propose a generic design based on multi-core processors and multi-queue network interface cards. We describe a prototype implementation and present an experimental evaluation of this design. We also devise a strategy for how to efficiently map packet forwarding and application processing tasks onto the multi-core architecture.","PeriodicalId":163079,"journal":{"name":"2012 IEEE 13th International Conference on High Performance Switching and Routing","volume":"105 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Improving performance in a combined router/server\",\"authors\":\"Voravit Tanyingyong, M. Hidell, Peter Sjödin\",\"doi\":\"10.1109/HPSR.2012.6260827\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A modern PC-based router can provide as competitive service as a specialized hardware router while offering more flexibility and possibility to extend beyond routing. We focus on a use case in which the PC-based router also functions as a server. In this paper, we propose a multi-core based architecture for a combined router/server that efficiently provides simultaneous packet forwarding and server processing. We improve the overall performance by creating a fast path for packet forwarding through caching flow entries in on-board classification hardware on the NIC. We propose a generic design based on multi-core processors and multi-queue network interface cards. We describe a prototype implementation and present an experimental evaluation of this design. We also devise a strategy for how to efficiently map packet forwarding and application processing tasks onto the multi-core architecture.\",\"PeriodicalId\":163079,\"journal\":{\"name\":\"2012 IEEE 13th International Conference on High Performance Switching and Routing\",\"volume\":\"105 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-06-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE 13th International Conference on High Performance Switching and Routing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HPSR.2012.6260827\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE 13th International Conference on High Performance Switching and Routing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HPSR.2012.6260827","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A modern PC-based router can provide as competitive service as a specialized hardware router while offering more flexibility and possibility to extend beyond routing. We focus on a use case in which the PC-based router also functions as a server. In this paper, we propose a multi-core based architecture for a combined router/server that efficiently provides simultaneous packet forwarding and server processing. We improve the overall performance by creating a fast path for packet forwarding through caching flow entries in on-board classification hardware on the NIC. We propose a generic design based on multi-core processors and multi-queue network interface cards. We describe a prototype implementation and present an experimental evaluation of this design. We also devise a strategy for how to efficiently map packet forwarding and application processing tasks onto the multi-core architecture.