输入电压摆幅对自应力测试仪估计的0.18 /spl mu/m NMOS老化的影响

ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095) Pub Date : 2000-03-13 DOI:10.1109/ICMTS.2000.844425

S. Chetlur, J. Zaneski, L. Mullin, A. Oates, R. Ashton, H. Chew, J. Zhou

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引用次数: 0

摘要

采用自应力测试仪研究了输入电压摆幅对逆变器中0.18 NMOS器件老化行为的影响。当输入脉冲的频率和上升/下降时间改变时，我们证明了每个时钟周期的有效老化时间't/sub /'随上升/下降跃迁而变化，这是决定NMOS退化的主要因素。

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Influence of input voltage swing on 0.18 /spl mu/m NMOS aging estimated by self-stressing testers

Self-stressing testers are used to study the impact of input voltage swing on the aging behavior of 0.18 NMOS devices in inverters. When the frequency and rise/fall time of the input pulse are altered, we demonstrate that the effective aging time 't/sub eff/' per clock cycle varies with the rise/fall transitions and is the main factor in deciding NMOS degradation.

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ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)

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