基于分解逻辑的高速Baugh-Wooley乘法器FPGA实现

ChemRN: Materials Processing (Topic) Pub Date : 2015-08-10 DOI:10.5121/eeiej.2015.2301

A. Kiran, Navdeep Prashar

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引用次数: 3

摘要

Baugh-Wooley算法是一种在数字信号处理应用中进行乘法运算的著名迭代算法。分解逻辑与Baugh-Wooley算法相结合，提高了速度，减少了关键路径延迟。本文利用分解逻辑和Baugh-Wooley算法设计并实现了高速乘法器。结果与展位乘数进行比较。提出了基于FPGA的结构，并在Xilinx 12.3器件上实现了设计。

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FPGA Implementation of High Speed Baugh-Wooley Multiplier Using Decomposition Logic

The Baugh-Wooley algorithm is a well-known iterative algorithm for performing multiplication in digital signal processing applications. Decomposition logic is used with Baugh-Wooley algorithm to enhance the speed and to reduce the critical path delay. In this paper a high speed multiplier is designed and implemented using decomposition logic and Baugh-Wooley algorithm. The result is compared with booth multiplier. FPGA based architecture is presented and design has been implemented using Xilinx 12.3 device.

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ChemRN: Materials Processing (Topic)

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