A register pressure sensitive instruction scheduler for dynamic issue processors

Several modern superscalar processors contain an out-of-order (OOO) instruction issue mechanism, which resolves dependencies between instructions to expose greater instruction-level parallelism (ILP). How to extend a traditional instruction scheduler to take advantage of these hardware resources has presented both a challenge and an opportunity for compiler design. In this paper, we present a new approach for instruction scheduling, which reorders the instructions in a traditional instruction schedule to reduce its register pressure while maintaining the amount of ILP exploitable by the target OOO processor. This may prevent the introduction of spill code, thus producing a performance improvement. We have implemented our instruction scheduler under the MOST scheduling testbed. Our experiments show that the proposed approach reduces the register pressure by 12.81% in SPEC92 benchmark loops which do not require any spill code. For loops with a high register pressure, our approach reduced the amount of spill code required by an average of 32.08% and produced an average performance improvement of 8.79%.