利用后门偏置增强平面FD和UTBB SOI晶体管自级联码结构的模拟性能

2015 30th Symposium on Microelectronics Technology and Devices (SBMicro) Pub Date : 2015-10-15 DOI:10.1109/SBMICRO.2015.7298134

R. Doria, D. Flandre, R. Trevisoli, M. de Souza, M. Pavanello

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引用次数: 2

摘要

本文首次报道了利用反向偏置提高由平面FD和UTBB SOI mosfet组成的自级联码结构的固有电压增益。结果显示，当漏极侧晶体管施加正向反偏置或源侧器件施加反向反偏置时，电压增益提高大于10 dB。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Use of back gate bias to enhance the analog performance of planar FD and UTBB SOI transistors-based self-cascode structures

This paper reports, for the first time, the use of back gate bias to improve the intrinsic voltage gain of self-cascode structures composed by planar FD and UTBB SOI MOSFETs. It is shown a voltage gain improvement larger than 10 dB when either a forward back bias is applied to the drain-side transistor or a reverse back bias is applied to the source side device.

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2015 30th Symposium on Microelectronics Technology and Devices (SBMicro)

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