An energy efficient multi-rate QC-LDPC decoder

This paper introduces, an energy efficient multirate decoder architecture for quasi-cyclic low-density parity-check (QC-LDPC) codes. To achieve good error correcting performance with lower complexity, an improved normalized min-sum algorithm with row-merge scheme is adopted. By exploring the properties of the layered decoding scheme, an enhanced QC-LDPC code with overlapped matrix is employed to offer adequate flexibility for parallel degree optimization and convergence speed. This in turn reduces the linear encoding complexity and data correlation problems during the multi-rate operations of the proposed decoder. Furthermore, to avoid memory access conflicts without increasing the hardware resources, eDRAM is utilized. By utilizing eDRAM, the overall memory bandwidth requisite is reduced considerably along with the inter-connect complexity and hardware overhead. This overall multi-rate decoder is designed and implemented using TSMC 65nm GP CMOS Technology to support all the code rates of IEEE 802.16e applications. From the implementation results it is observed that the designed multi-rate decoder attains improved throughput-to-area ratio (TAR) with less power consumption when analysed with other multi-rate decoders.