{"title":"GF(2)数学协处理器的研制","authors":"R. Tervo","doi":"10.1109/CCECE.2019.8861747","DOIUrl":null,"url":null,"abstract":"The mathematics of Galois fields GF(2) and the extension fields GF(2m) underpin applications in error control coding and cryptology yet these binary operations are not directly supported in most digital computer instruction sets. A set of hardware blocks to perform low level GF(2) operations as a math coprocessor is described. The circuits were elaborated in VHDL and integrated into an FPGA-based soft processor (Nios II). Performance tests and detailed timing measurements are reported for typical GF(2) calculations.","PeriodicalId":352860,"journal":{"name":"2019 IEEE Canadian Conference of Electrical and Computer Engineering (CCECE)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Development of a GF(2)Math Coprocessor\",\"authors\":\"R. Tervo\",\"doi\":\"10.1109/CCECE.2019.8861747\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The mathematics of Galois fields GF(2) and the extension fields GF(2m) underpin applications in error control coding and cryptology yet these binary operations are not directly supported in most digital computer instruction sets. A set of hardware blocks to perform low level GF(2) operations as a math coprocessor is described. The circuits were elaborated in VHDL and integrated into an FPGA-based soft processor (Nios II). Performance tests and detailed timing measurements are reported for typical GF(2) calculations.\",\"PeriodicalId\":352860,\"journal\":{\"name\":\"2019 IEEE Canadian Conference of Electrical and Computer Engineering (CCECE)\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-05-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE Canadian Conference of Electrical and Computer Engineering (CCECE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CCECE.2019.8861747\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE Canadian Conference of Electrical and Computer Engineering (CCECE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CCECE.2019.8861747","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The mathematics of Galois fields GF(2) and the extension fields GF(2m) underpin applications in error control coding and cryptology yet these binary operations are not directly supported in most digital computer instruction sets. A set of hardware blocks to perform low level GF(2) operations as a math coprocessor is described. The circuits were elaborated in VHDL and integrated into an FPGA-based soft processor (Nios II). Performance tests and detailed timing measurements are reported for typical GF(2) calculations.
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