一种10位50毫秒/秒的SAR ADC，采用了降低基准电压缓冲器驱动能力要求的技术

2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2013-12-23 DOI:10.1109/ASSCC.2013.6691040

Shao-Hua Wan, Che-Hsun Kuo, Soon-Jyh Chang, Guan-Ying Huang, Chun-Po Huang, Goh Jih Ren, Kai-Tzeng Chiou, C. Ho

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引用次数: 22

摘要

高速逐次逼近(SAR) ADC需要具有高驱动能力的参考电压缓冲器。此外，参考缓冲器的功耗通常比SAR ADC本身的功耗大几倍。采用了三种技术来降低SAR adc对基准电压缓冲器驱动能力的要求。提出了一种基于上述技术的10b50ms /s ADC。原型ADC采用40nm LP 1P7M CMOS技术制作。在1.1V电源电压50 MS/s下，功耗为0.47 mW, ENOB为9.18 bit, FoM为16 fJ/转换步长。活动面积为0.0114 mm2。

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A 10-bit 50-MS/s SAR ADC with techniques for relaxing the requirement on driving capability of reference voltage buffers

A high speed successive approximation (SAR) ADC requires reference voltage buffers with high driving capability. Moreover, the power consumption of the reference buffers is usually several times larger than that of the SAR ADC itself. Three techniques are adopted to mitigate the requirement on driving capability of reference voltage buffers for SAR ADCs. A 10b 50MS/s ADC based on the proposed techniques is presented. The prototype ADC was fabricated in 40nm LP 1P7M CMOS technology. It consumes 0.47 mW at 50 MS/s from 1.1V supply voltage and achieves ENOB of 9.18-bit and figure of merit (FoM) of 16 fJ/conversion-step. The active area is 0.0114 mm2.

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2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)

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