一种支持运行时估计和补偿的时间-数字转换器的新型FPGA实现

Van Luan Dinh, X. Nguyen, Hyuk-Jae Lee
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引用次数: 2

摘要

时间-数字转换器(tdc)广泛应用于需要测量事件之间时间间隔的应用中。在以前使用反馈回路和延长延迟线的设计中,过程电压-温度(PVT)的变化通常会降低测量的准确性。为了克服PVT变化带来的精度损失,本研究提出了一种基于运行时估计和PVT变化补偿的可合成TDC设计。由一系列缓冲器组成的延迟线用于检测用于测量两个事件之间时间间隔的环形振荡器的周期。通过比较检测周期和系统时钟,在运行时补偿振荡周期的变化。采用低成本的Xilinx Spartan-6 LX9 FPGA和50 mhz振荡器成功实现了TDC。实验结果表明,该TDC对PVT变化具有较强的鲁棒性,分辨率为19.1 ps。与之前的设计相比,该TDC在参考时钟的面积、分辨率和频率方面的折衷性提高了约5倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Novel FPGA Implementation of a Time-to-Digital Converter Supporting Run-Time Estimation and Compensation
Time-to-digital converters (TDCs) are widely used in applications that require the measurement of the time interval between events. In previous designs using a feedback loop and an extended delay line, process-voltage-temperature (PVT) variation often decreases the accuracy of measurements. To overcome the loss of accuracy caused by PVT variation, this study proposes a novel design of a synthesizable TDC that employs run-time estimation and compensation of PVT variation. A delay line consisting of a series of buffers is used to detect the period of a ring oscillator designed to measure the time interval between two events. By comparing the detected period and the system clock, the variation of the oscillation period is compensated at run-time. The proposed TDC is successfully implemented by using a low-cost Xilinx Spartan-6 LX9 FPGA with a 50-MHz oscillator. Experimental results show that the proposed TDC is robust to PVT variation with a resolution of 19.1 ps. In comparison with previous design, the proposed TDC achieves about five times better tradeoff in the area, resolution, and frequency of the reference clock.
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