{"title":"单次全屏硬件加速抗锯齿","authors":"Jin-Aeon Lee, L. Kim","doi":"10.1145/346876.348225","DOIUrl":null,"url":null,"abstract":"This paper describes a modified A-buffer algorithm and its hardware architecture for single-pass full-screen antialiasing. For storage and management of fragments, a dynamic memory management scheme, which can be efficiently implemented by hardware is introduced. In the fragment resolving stage, a subpixel color-blending scheme that resolves subpixels simultaneously is used to correctly blend transparencies and resolve intersections of polygons in a pixel. A rasterization processor architecture, which can process multiple pixels simultaneously, is also presented. CR","PeriodicalId":298241,"journal":{"name":"Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware","volume":"111 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"Single-pass full-screen hardware accelerated antialiasing\",\"authors\":\"Jin-Aeon Lee, L. Kim\",\"doi\":\"10.1145/346876.348225\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a modified A-buffer algorithm and its hardware architecture for single-pass full-screen antialiasing. For storage and management of fragments, a dynamic memory management scheme, which can be efficiently implemented by hardware is introduced. In the fragment resolving stage, a subpixel color-blending scheme that resolves subpixels simultaneously is used to correctly blend transparencies and resolve intersections of polygons in a pixel. A rasterization processor architecture, which can process multiple pixels simultaneously, is also presented. CR\",\"PeriodicalId\":298241,\"journal\":{\"name\":\"Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware\",\"volume\":\"111 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/346876.348225\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/346876.348225","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper describes a modified A-buffer algorithm and its hardware architecture for single-pass full-screen antialiasing. For storage and management of fragments, a dynamic memory management scheme, which can be efficiently implemented by hardware is introduced. In the fragment resolving stage, a subpixel color-blending scheme that resolves subpixels simultaneously is used to correctly blend transparencies and resolve intersections of polygons in a pixel. A rasterization processor architecture, which can process multiple pixels simultaneously, is also presented. CR