{"title":"具有电压模式模拟自旋算子的20x28自旋混合内存退火计算机用于解决组合优化问题","authors":"Junjie Mu, Yuqi Su, Bongjin Kim","doi":"10.23919/VLSICircuits52068.2021.9492453","DOIUrl":null,"url":null,"abstract":"Computationally-expensive combinatorial optimization problems can be solved effectively via finding the ground state of the system by annealing computers. This work proposes a hybrid analog-digital implementation of an annealing computer that achieves 1.58x improvement in the area and >3x reduction in annealing time compared with recent works. The test-chip is fabricated using the 65nm process, and the measured power consumption is 9.9mW at 0.8V and 320MHZ.","PeriodicalId":106356,"journal":{"name":"2021 Symposium on VLSI Circuits","volume":"66 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A 20x28 Spins Hybrid In-Memory Annealing Computer Featuring Voltage-Mode Analog Spin Operator for Solving Combinatorial Optimization Problems\",\"authors\":\"Junjie Mu, Yuqi Su, Bongjin Kim\",\"doi\":\"10.23919/VLSICircuits52068.2021.9492453\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Computationally-expensive combinatorial optimization problems can be solved effectively via finding the ground state of the system by annealing computers. This work proposes a hybrid analog-digital implementation of an annealing computer that achieves 1.58x improvement in the area and >3x reduction in annealing time compared with recent works. The test-chip is fabricated using the 65nm process, and the measured power consumption is 9.9mW at 0.8V and 320MHZ.\",\"PeriodicalId\":106356,\"journal\":{\"name\":\"2021 Symposium on VLSI Circuits\",\"volume\":\"66 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSICircuits52068.2021.9492453\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSICircuits52068.2021.9492453","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 20x28 Spins Hybrid In-Memory Annealing Computer Featuring Voltage-Mode Analog Spin Operator for Solving Combinatorial Optimization Problems
Computationally-expensive combinatorial optimization problems can be solved effectively via finding the ground state of the system by annealing computers. This work proposes a hybrid analog-digital implementation of an annealing computer that achieves 1.58x improvement in the area and >3x reduction in annealing time compared with recent works. The test-chip is fabricated using the 65nm process, and the measured power consumption is 9.9mW at 0.8V and 320MHZ.
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