全集成k波段CMOS功率放大器,Psat为23.8 dBm, PAE为25.1%

Y. Kawano, A. Mineyama, Toshihide Suzuki, Masaru Sato, T. Hirose, K. Joshin
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引用次数: 26

摘要

设计了一种基于65nm CMOS的全集成k波段差分功率放大器。由二级级联码结构组成的功率放大器具有基于变压器的匹配网络。为匹配阻抗,各变压器的输入级匝比设计为1∶1,级间匝比设计为2∶1,输出级匝比设计为1∶1.5。在16ghz ~ 25ghz频段内获得了大于20dbm的饱和功率。饱和功率峰值为23.8 dBm,功率附加效率(PAE)为25.1%。包括直流焊盘和射频焊盘在内的芯片占用面积为1.2 × 0.8 mm。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A fully-integrated K-band CMOS power amplifier with Psat of 23.8 dBm and PAE of 25.1 %
A fully-integrated K-band differential power amplifier was designed in 65 nm CMOS. The power amplifier comprised of the 2-stage cascode configuration has the matching networks based on the transformer. To match the impedances, turn ratios of each transformer were designed to be 1∶1 for the input stage, 2∶1 for the inter stage, and 1∶1.5 for the output stage, respectively. The saturation power of more than 20 dBm was obtained in the band between 16 GHz and 25 GHz. The peak value of the saturation power was 23.8 dBm, and the power added efficiency (PAE) was 25.1 % at 19 GHz. The chip occupied area including the DC and RF pads is 1.2 × 0.8 mm.
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