高效深度学习推理的FPGA逻辑块架构

Mohamed Eldafrawy, Andrew Boutros, S. Yazdanshenas, Vaughn Betz
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引用次数: 21

摘要

与半精度或单精度浮点相比,降低深度神经网络(DNN)推理加速器的精度可以产生很大的效率提升,而精度几乎没有下降,因为每单位面积可以实现更多的乘法运算。广泛的精度落在硬件效率与精度的帕累托最优曲线上,没有单一精度占主导地位,这使得fpga的可变精度能力非常有价值。我们提出了三种类型的逻辑块架构增强,并全面评估了六种架构,这些架构可以提高在软结构中实现的乘法和加法的面积效率。增加LUT可断裂性并在ALM(4位加法器双链架构)中添加两个加法器,可使算术重型机器学习(ML)内核的面积减少1.5倍,同时提高其速度。此外,该架构还将一般应用程序的逻辑面积减少了6%,而关键路径延迟仅增加了1%。然而,我们的最高影响选项,即在逻辑簇中添加9位阴影乘法器,分别将ML内核的面积和关键路径延迟减少了2.4倍和1.2倍。这些巨大的增益是以一般应用增加15%的逻辑面积为代价的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
FPGA Logic Block Architectures for Efficient Deep Learning Inference
Reducing the precision of deep neural network (DNN) inference accelerators can yield large efficiency gains with little or no accuracy degradation compared to half or single precision floating-point by enabling more multiplication operations per unit area. A wide range of precisions fall on the pareto-optimal curve of hardware efficiency vs. accuracy with no single precision dominating, making the variable precision capabilities of FPGAs very valuable. We propose three types of logic block architectural enhancements and fully evaluate a total of six architectures that improve the area efficiency of multiplications and additions implemented in the soft fabric. Increasing the LUT fracturability and adding two adders to the ALM (4-bit Adder Double Chain architecture) leads to a 1.5× area reduction for arithmetic heavy machine learning (ML) kernels, while increasing their speed. In addition, this architecture also reduces the logic area of general applications by 6%, while increasing the critical path delay by only 1%. However, our highest impact option, which adds a 9-bit shadow multiplier to the logic clusters, reduces the area and critical path delay of ML kernels by 2.4× and 1.2×, respectively. These large gains come at a cost of 15% logic area increase for general applications.
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