Accurate yield estimation of read access failure sram

This work is focused on accurate calculation SRAM bitline voltage difference as main source of read access failure for deep submicron CMOS design. Accurate estimation minimal voltage difference allows increase memory performance and provide sufficient memory yield. We are considering a worst-case analysis that accounts for weak cells, and presents guidelines to achieve high yield has been proposed, but this method is too pessimistic and results in reduced performance of SRAM. A method to predict the yield of a memory chip based on the cell-failure probability is proposed in our work. The proposed method based on conditional probability of read access failure relatively sense amplifier offset and bitline voltage difference. Obtained experimental results show that discharge time is needed to get a minimal voltage difference can be reduce from 14,5 to 18,1% in 90 nm technological nodes.