{"title":"PLASMA: FSM设计内核","authors":"R. Puri, M. Hasan","doi":"10.1109/ASIC.1990.186202","DOIUrl":null,"url":null,"abstract":"A state machine synthesis system, named PLASMA, which can be used for the implementation of finite-state machines (FSMs) in programmable logic arrays (PLAs) is discussed. The minimization algorithm effectively prunes the tree structure of compatibles list to find the minimum form of a minimized single output change (SOC) machine. State assignment, i.e. the process of binary encoding of internal states of the FSM, has been efficiently utilized to save the silicon area occupied by PLA. The system is complete and works efficiently for incompletely specified sequential machines (ISSMs) to achieve area optimization in the PLA structure.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"238 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"PLASMA: a FSM design kernel\",\"authors\":\"R. Puri, M. Hasan\",\"doi\":\"10.1109/ASIC.1990.186202\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A state machine synthesis system, named PLASMA, which can be used for the implementation of finite-state machines (FSMs) in programmable logic arrays (PLAs) is discussed. The minimization algorithm effectively prunes the tree structure of compatibles list to find the minimum form of a minimized single output change (SOC) machine. State assignment, i.e. the process of binary encoding of internal states of the FSM, has been efficiently utilized to save the silicon area occupied by PLA. The system is complete and works efficiently for incompletely specified sequential machines (ISSMs) to achieve area optimization in the PLA structure.<<ETX>>\",\"PeriodicalId\":126693,\"journal\":{\"name\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"volume\":\"238 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-09-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1990.186202\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1990.186202","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A state machine synthesis system, named PLASMA, which can be used for the implementation of finite-state machines (FSMs) in programmable logic arrays (PLAs) is discussed. The minimization algorithm effectively prunes the tree structure of compatibles list to find the minimum form of a minimized single output change (SOC) machine. State assignment, i.e. the process of binary encoding of internal states of the FSM, has been efficiently utilized to save the silicon area occupied by PLA. The system is complete and works efficiently for incompletely specified sequential machines (ISSMs) to achieve area optimization in the PLA structure.<>
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