超大规模集成电路Imagine处理器的设计与验证

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 2002-09-16 DOI:10.1109/ICCD.2002.1106784

Brucek Khailany, W. Dally, Andrew Chang, U. Kapasi, Jinyung Namkoong, Brian Towles

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引用次数: 33

摘要

Imagine流处理器是一个2100万个晶体管芯片，由斯坦福大学和德州仪器合作，采用1.5 V 0.15 /spl mu/m工艺，采用五层铝金属。介绍了Imagine处理器的VLSI设计、时钟和验证方法。这些方法使一个资源有限的研究生小组能够在现代ASIC流程中设计出高性能的媒体处理器。

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VLSI design and verification of the Imagine processor

The Imagine stream processor is a 21 million transistor chip implemented by a collaboration between Stanford University and Texas Instruments in a 1.5 V 0.15 /spl mu/m process with five layers of aluminum metal. The VLSI design, clocking, and verification methodologies for the Imagine processor are presented. These methodologies enabled a small team of graduate students with limited resources to design a high-performance media processor in a modern ASIC flow.

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来源期刊

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors

CiteScore

2.30

自引率

0.00%

发文量