{"title":"并行gpu加速尖峰排序","authors":"Ian Schofield, A. Alimohammad","doi":"10.1109/CCECE.2019.8861978","DOIUrl":null,"url":null,"abstract":"A neural spike sorting system has been modeled and implemented using a massively-parallel graphics processing unit (GPU). The spike sorting software consists of three stages: spike detection, feature detection, and clustering developed utilizing algorithms suitable for masssively parallel GPU architectures. The spike sorting system was developed using software engineering principles of portability and maintainability with the goal of determining achievable performance speedup over the same software implemented in MATLAB on a multi-core processor. We consider the challenges of converting multiple-unit neural activity into single-unit activity suitable for brain-machine interfacing (BMI) using spike sorting algorithms.","PeriodicalId":352860,"journal":{"name":"2019 IEEE Canadian Conference of Electrical and Computer Engineering (CCECE)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Parallel GPU-Accelerated Spike Sorting\",\"authors\":\"Ian Schofield, A. Alimohammad\",\"doi\":\"10.1109/CCECE.2019.8861978\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A neural spike sorting system has been modeled and implemented using a massively-parallel graphics processing unit (GPU). The spike sorting software consists of three stages: spike detection, feature detection, and clustering developed utilizing algorithms suitable for masssively parallel GPU architectures. The spike sorting system was developed using software engineering principles of portability and maintainability with the goal of determining achievable performance speedup over the same software implemented in MATLAB on a multi-core processor. We consider the challenges of converting multiple-unit neural activity into single-unit activity suitable for brain-machine interfacing (BMI) using spike sorting algorithms.\",\"PeriodicalId\":352860,\"journal\":{\"name\":\"2019 IEEE Canadian Conference of Electrical and Computer Engineering (CCECE)\",\"volume\":\"124 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-05-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE Canadian Conference of Electrical and Computer Engineering (CCECE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CCECE.2019.8861978\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE Canadian Conference of Electrical and Computer Engineering (CCECE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CCECE.2019.8861978","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A neural spike sorting system has been modeled and implemented using a massively-parallel graphics processing unit (GPU). The spike sorting software consists of three stages: spike detection, feature detection, and clustering developed utilizing algorithms suitable for masssively parallel GPU architectures. The spike sorting system was developed using software engineering principles of portability and maintainability with the goal of determining achievable performance speedup over the same software implemented in MATLAB on a multi-core processor. We consider the challenges of converting multiple-unit neural activity into single-unit activity suitable for brain-machine interfacing (BMI) using spike sorting algorithms.