{"title":"伪穷举测试中组合电路划分的一种有效算法","authors":"M. El-Mahlawy, W. Waller","doi":"10.1109/NRSC.2000.838953","DOIUrl":null,"url":null,"abstract":"We have presented an efficient algorithm to partition the combinational circuits for built-in pseudoexhaustive self-testing of VLSI circuits. The partitioning procedure is based on several heuristics that enable the procedure to overcome the unexpected results of the greedy heuristic procedure.","PeriodicalId":211510,"journal":{"name":"Proceedings of the Seventeenth National Radio Science Conference. 17th NRSC'2000 (IEEE Cat. No.00EX396)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"An efficient algorithm to partition the combinational circuits for pseudoexhaustive testing\",\"authors\":\"M. El-Mahlawy, W. Waller\",\"doi\":\"10.1109/NRSC.2000.838953\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We have presented an efficient algorithm to partition the combinational circuits for built-in pseudoexhaustive self-testing of VLSI circuits. The partitioning procedure is based on several heuristics that enable the procedure to overcome the unexpected results of the greedy heuristic procedure.\",\"PeriodicalId\":211510,\"journal\":{\"name\":\"Proceedings of the Seventeenth National Radio Science Conference. 17th NRSC'2000 (IEEE Cat. No.00EX396)\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-02-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the Seventeenth National Radio Science Conference. 17th NRSC'2000 (IEEE Cat. No.00EX396)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NRSC.2000.838953\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the Seventeenth National Radio Science Conference. 17th NRSC'2000 (IEEE Cat. No.00EX396)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NRSC.2000.838953","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An efficient algorithm to partition the combinational circuits for pseudoexhaustive testing
We have presented an efficient algorithm to partition the combinational circuits for built-in pseudoexhaustive self-testing of VLSI circuits. The partitioning procedure is based on several heuristics that enable the procedure to overcome the unexpected results of the greedy heuristic procedure.