J. I. Morales, F. Chierchie, P. Mandolesi, E. Paolini
{"title":"用于ISM波段的FPGA RF PWM调制器","authors":"J. I. Morales, F. Chierchie, P. Mandolesi, E. Paolini","doi":"10.1109/CAE56623.2023.10086975","DOIUrl":null,"url":null,"abstract":"Two all-digital transmitter architectures with distortion-free pulse width modulation are presented in this work. The modulation achieves a clean spectrum free of spurious even when a low number of quantization levels are used, allowing their implementation using clock-based schemes on general purposes FPGAs. The influence of the oversampling on the performance is evaluated in terms of the adjacent channel power ratio (ACPR) for different values of time resolution. Values of ACPR1 and ACPR2 better than −45 dBc and −42 dBc, respectively, are achieved using only 11 resolution time steps in the binary signal and an oversampling ratio between the carrier and baseband signal frequencies of 64. The architectures are verified by FPGA implementations using 64-QAM modulated signal and carrier frequencies in two ISM bands (13.56 MHz and 40.68 MHz), utilizing less than 1% of the available resources.","PeriodicalId":212534,"journal":{"name":"2023 Argentine Conference on Electronics (CAE)","volume":"167 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An FPGA RF PWM Modulator for ISM Bands\",\"authors\":\"J. I. Morales, F. Chierchie, P. Mandolesi, E. Paolini\",\"doi\":\"10.1109/CAE56623.2023.10086975\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Two all-digital transmitter architectures with distortion-free pulse width modulation are presented in this work. The modulation achieves a clean spectrum free of spurious even when a low number of quantization levels are used, allowing their implementation using clock-based schemes on general purposes FPGAs. The influence of the oversampling on the performance is evaluated in terms of the adjacent channel power ratio (ACPR) for different values of time resolution. Values of ACPR1 and ACPR2 better than −45 dBc and −42 dBc, respectively, are achieved using only 11 resolution time steps in the binary signal and an oversampling ratio between the carrier and baseband signal frequencies of 64. The architectures are verified by FPGA implementations using 64-QAM modulated signal and carrier frequencies in two ISM bands (13.56 MHz and 40.68 MHz), utilizing less than 1% of the available resources.\",\"PeriodicalId\":212534,\"journal\":{\"name\":\"2023 Argentine Conference on Electronics (CAE)\",\"volume\":\"167 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-03-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 Argentine Conference on Electronics (CAE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CAE56623.2023.10086975\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 Argentine Conference on Electronics (CAE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CAE56623.2023.10086975","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Two all-digital transmitter architectures with distortion-free pulse width modulation are presented in this work. The modulation achieves a clean spectrum free of spurious even when a low number of quantization levels are used, allowing their implementation using clock-based schemes on general purposes FPGAs. The influence of the oversampling on the performance is evaluated in terms of the adjacent channel power ratio (ACPR) for different values of time resolution. Values of ACPR1 and ACPR2 better than −45 dBc and −42 dBc, respectively, are achieved using only 11 resolution time steps in the binary signal and an oversampling ratio between the carrier and baseband signal frequencies of 64. The architectures are verified by FPGA implementations using 64-QAM modulated signal and carrier frequencies in two ISM bands (13.56 MHz and 40.68 MHz), utilizing less than 1% of the available resources.