{"title":"利用脉冲发生器设计具有一致环路带宽的基于环压控振荡器的砰砰锁相环/CDR研究","authors":"W. Bae, D. Jeong","doi":"10.1109/ELINFOCOM.2014.6914430","DOIUrl":null,"url":null,"abstract":"A technique making the loop bandwidth consistent against PVT variations in the ring-VCO based bang-bang PLL/CDR is proposed. Pulse generators are used to implement this technique by cancelling out PVT sensitivity of the ring-VCO. Simulation results show that the loop bandwidth variation is reduced by half with the proposed technique. Also, by using the pulse generators, the loop filter capacitor area is reduced.","PeriodicalId":360207,"journal":{"name":"2014 International Conference on Electronics, Information and Communications (ICEIC)","volume":"340 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A study on using pulse generators to design a ring-VCO based bang-bang PLL/CDR with a consistent loop bandwidth\",\"authors\":\"W. Bae, D. Jeong\",\"doi\":\"10.1109/ELINFOCOM.2014.6914430\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A technique making the loop bandwidth consistent against PVT variations in the ring-VCO based bang-bang PLL/CDR is proposed. Pulse generators are used to implement this technique by cancelling out PVT sensitivity of the ring-VCO. Simulation results show that the loop bandwidth variation is reduced by half with the proposed technique. Also, by using the pulse generators, the loop filter capacitor area is reduced.\",\"PeriodicalId\":360207,\"journal\":{\"name\":\"2014 International Conference on Electronics, Information and Communications (ICEIC)\",\"volume\":\"340 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-10-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 International Conference on Electronics, Information and Communications (ICEIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ELINFOCOM.2014.6914430\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 International Conference on Electronics, Information and Communications (ICEIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ELINFOCOM.2014.6914430","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A study on using pulse generators to design a ring-VCO based bang-bang PLL/CDR with a consistent loop bandwidth
A technique making the loop bandwidth consistent against PVT variations in the ring-VCO based bang-bang PLL/CDR is proposed. Pulse generators are used to implement this technique by cancelling out PVT sensitivity of the ring-VCO. Simulation results show that the loop bandwidth variation is reduced by half with the proposed technique. Also, by using the pulse generators, the loop filter capacitor area is reduced.