Implementation of Area Efficient Pipelined R22SDF FFT Architecture

This paper presents the analysis of various architectures of Low power FFT Processors. FFT is a major building block in DSP and communication system. FFT is an efficient way to implement DFT in a faster manner. Using FFT the number of multiplication and addition order O(N/2log2N) and O(Nlog2N) are reduced. Conventional FFT has more chip area and delay. Hence pipelined FFT is preferred to overcome the demerits of the conventional processor. This paper reports a detailed study of various FFT architectures and mainly about R22SDF SDF FFT. In this paper, to reduce delay an advanced design of 64-point Pipelined Radix 22 Single Path Delay Feedback (R22SDF) FFT architecture has been proposed by using Verilog Hardware Description Language (Verilog HDL). The simulation results has been evaluated by using Modelsim 6.3C and synthesis results are estimated by using Xilinx Planahead 12.4i design tool.