Compressor Using Full Swing XOR Logic Gate

Compressors are generally used in the second stage of Multiplier i.e. in the reduction of partial products stage, which majorly contributes to the power consumption and delay of the Multiplier. Therefore, Compressor module should be designed efficiently to deliver the best performance in all the aspects. This work introduces a 7:3 Compressor using Full Swing XOR Logic Gate. Various topologies of XOR logic gate using Complementary Pass Transistor logic (CPL), Double Pass Transistor logic (DPL), Feedback based XOR logic gate, Conventional series parallel XOR logic gate, Mirror XOR logic gate and Full Swing XOR logic gate are designed and implemented using gpdk45 models in Cadence Virtuoso at supply voltage of 0.5 V. The performance of these topologies of XOR logic gates is analyzed in terms of delay and average power. It is observed that the Full Swing XOR Logic Gate shows optimum performance in terms of rise time, fall time and average power with respect to the output capacitance contribution. As an application, the 7:3 Compressor is designed using Conventional XOR logic gate, Mirror XOR logic gate and the Full Swing XOR logic gate individually. The performance of these three ways of implementation of 7:3 Compressor is analyzed using gpdk45 models in Cadence Virtuoso at 0.5 V of supply voltage. The analysis shows reduction of 26.28% & 25.44% in average power for 7:3 Compressor using Full Swing XOR gate than the same using Conventional & Mirror XOR logic gates respectively.