Verification and test challenges in SoC designs

SoC (system-on-chip) designs have introduced several new challenges for the functional verification and test disciplines. Besides the ever-growing functional complexity, we need to manage from several clock domains and low-power modes to all sorts of IP blocks like processors, complex peripherals, analog functions and different kinds of embedded memories. The reuse of 3/sup rd/ party IP may help accelerating the design of new products, but it usually does not help the functional verification and it may even add to its complexity. The same die may be used in several packages with a different number of pins and bond-out options. This presentation discusses these and other verification and test challenges. It also describes what tools, techniques and methodologies the industry is currently using to cope with them, and finalizes outlining some future directions.