{"title":"用于高性能时钟的1V, 1mW, 4GHz注入锁定振荡器","authors":"Lin Zhang, B. Ciftcioglu, Hui Wu","doi":"10.1109/CICC.2007.4405740","DOIUrl":null,"url":null,"abstract":"Injection-locked clocking (ILC) has been proposed previously to improve the skew and jitter performance while reducing the power consumption in multi-gigahertz clock distribution networks. This paper presents a new design of the injection-locked oscillator (ILO) suitable for ILC applications. It uses a transformer to generate differential signals and then directly inject them into the ILO core. It also incorporates a switched-capacitor array for frequency tuning and hence digital deskew in ILC. A 4 GHz test chip was designed and fabricated in a 0.18 mum standard digital CMOS. It consists of four ILOs driven by a balanced H-tree. Each ILO consumes less than 1 mW from a 1 V power supply. 5-bit digital deskew achieves 55 ps delay tuning range and 1.8 ps resolution. Measurement shows that only 30 fs cycle-to-cycle jitter degradation was introduced and no phase noise degradation at frequency offset up to 600 kHz.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"214 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"A 1V, 1mW, 4GHz Injection-Locked Oscillator for High-Performance Clocking\",\"authors\":\"Lin Zhang, B. Ciftcioglu, Hui Wu\",\"doi\":\"10.1109/CICC.2007.4405740\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Injection-locked clocking (ILC) has been proposed previously to improve the skew and jitter performance while reducing the power consumption in multi-gigahertz clock distribution networks. This paper presents a new design of the injection-locked oscillator (ILO) suitable for ILC applications. It uses a transformer to generate differential signals and then directly inject them into the ILO core. It also incorporates a switched-capacitor array for frequency tuning and hence digital deskew in ILC. A 4 GHz test chip was designed and fabricated in a 0.18 mum standard digital CMOS. It consists of four ILOs driven by a balanced H-tree. Each ILO consumes less than 1 mW from a 1 V power supply. 5-bit digital deskew achieves 55 ps delay tuning range and 1.8 ps resolution. Measurement shows that only 30 fs cycle-to-cycle jitter degradation was introduced and no phase noise degradation at frequency offset up to 600 kHz.\",\"PeriodicalId\":130106,\"journal\":{\"name\":\"2007 IEEE Custom Integrated Circuits Conference\",\"volume\":\"214 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2007.4405740\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2007.4405740","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1V, 1mW, 4GHz Injection-Locked Oscillator for High-Performance Clocking
Injection-locked clocking (ILC) has been proposed previously to improve the skew and jitter performance while reducing the power consumption in multi-gigahertz clock distribution networks. This paper presents a new design of the injection-locked oscillator (ILO) suitable for ILC applications. It uses a transformer to generate differential signals and then directly inject them into the ILO core. It also incorporates a switched-capacitor array for frequency tuning and hence digital deskew in ILC. A 4 GHz test chip was designed and fabricated in a 0.18 mum standard digital CMOS. It consists of four ILOs driven by a balanced H-tree. Each ILO consumes less than 1 mW from a 1 V power supply. 5-bit digital deskew achieves 55 ps delay tuning range and 1.8 ps resolution. Measurement shows that only 30 fs cycle-to-cycle jitter degradation was introduced and no phase noise degradation at frequency offset up to 600 kHz.