SOI超小口袋Si0.7Ge0.3无结隧道场效应管的表征

S. Tripathi, Shekhar Verma, Namrata Dhanda
{"title":"SOI超小口袋Si0.7Ge0.3无结隧道场效应管的表征","authors":"S. Tripathi, Shekhar Verma, Namrata Dhanda","doi":"10.1109/DEVIC.2019.8783891","DOIUrl":null,"url":null,"abstract":"The Tunnel FET has substantial potential to overcome limitations imposed due the scaling in low voltage region because of its steep subthreshold slope relative to its corresponding junction based MOSFET counterpart. Use of Si0.7Ge0.3 material as pocket region (0.5nm) enhances band-to-band tunneling by decreasing tunneling distance. The proposed pocket ultra small pocket Si0.7Ge0.3 Junction-less TFET(JLTFET) exploits advantage junction-less regions and p-type pocket region to improve device performance in subthreshold region showing improvement in subthreshold slope and better ON and OFF-state drain current ratio as compared to other similar TFET structures. Proposed ultra small pocket JLTFET shows high value $\\mathbf{I}_{\\mathbf{ON}}/\\mathbf{I}_{\\mathbf{OFF}}$ ratio and good subthreshold behaviour even with 2nm gate length and body thickness 0.5nm. All the designs proposed for n JLTFETs are designed on visual TCAD 2D/3D device simulator.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Characterisation of Ultra-Small Pocket Si0.7Ge0.3 Junction-less Tunnel FET with SOI\",\"authors\":\"S. Tripathi, Shekhar Verma, Namrata Dhanda\",\"doi\":\"10.1109/DEVIC.2019.8783891\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The Tunnel FET has substantial potential to overcome limitations imposed due the scaling in low voltage region because of its steep subthreshold slope relative to its corresponding junction based MOSFET counterpart. Use of Si0.7Ge0.3 material as pocket region (0.5nm) enhances band-to-band tunneling by decreasing tunneling distance. The proposed pocket ultra small pocket Si0.7Ge0.3 Junction-less TFET(JLTFET) exploits advantage junction-less regions and p-type pocket region to improve device performance in subthreshold region showing improvement in subthreshold slope and better ON and OFF-state drain current ratio as compared to other similar TFET structures. Proposed ultra small pocket JLTFET shows high value $\\\\mathbf{I}_{\\\\mathbf{ON}}/\\\\mathbf{I}_{\\\\mathbf{OFF}}$ ratio and good subthreshold behaviour even with 2nm gate length and body thickness 0.5nm. All the designs proposed for n JLTFETs are designed on visual TCAD 2D/3D device simulator.\",\"PeriodicalId\":294095,\"journal\":{\"name\":\"2019 Devices for Integrated Circuit (DevIC)\",\"volume\":\"50 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 Devices for Integrated Circuit (DevIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DEVIC.2019.8783891\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Devices for Integrated Circuit (DevIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DEVIC.2019.8783891","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

摘要

隧道场效应管具有巨大的潜力,可以克服由于在低压区缩放而造成的限制,因为相对于相应的基于结的MOSFET,隧道场效应管具有陡峭的亚阈值斜率。使用Si0.7Ge0.3材料作为口袋区(0.5nm),通过减小隧道距离来增强带间隧道。本文提出的口袋型超小口袋型Si0.7Ge0.3无结TFET(JLTFET)利用无结区和p型口袋区优势,提高了器件在亚阈值区域的性能,与其他类似的TFET结构相比,其亚阈值斜率有所改善,并且具有更好的ON和off状态漏极电流比。所提出的超小口袋JLTFET在栅极长度为2nm、体厚为0.5nm时,具有较高的$\mathbf{I}_{\mathbf{ON}}/\mathbf{I}_{\mathbf{OFF}}$比值和良好的亚阈值行为。所有jltfet的设计都是在可视化的TCAD 2D/3D器件模拟器上设计的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Characterisation of Ultra-Small Pocket Si0.7Ge0.3 Junction-less Tunnel FET with SOI
The Tunnel FET has substantial potential to overcome limitations imposed due the scaling in low voltage region because of its steep subthreshold slope relative to its corresponding junction based MOSFET counterpart. Use of Si0.7Ge0.3 material as pocket region (0.5nm) enhances band-to-band tunneling by decreasing tunneling distance. The proposed pocket ultra small pocket Si0.7Ge0.3 Junction-less TFET(JLTFET) exploits advantage junction-less regions and p-type pocket region to improve device performance in subthreshold region showing improvement in subthreshold slope and better ON and OFF-state drain current ratio as compared to other similar TFET structures. Proposed ultra small pocket JLTFET shows high value $\mathbf{I}_{\mathbf{ON}}/\mathbf{I}_{\mathbf{OFF}}$ ratio and good subthreshold behaviour even with 2nm gate length and body thickness 0.5nm. All the designs proposed for n JLTFETs are designed on visual TCAD 2D/3D device simulator.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信