{"title":"SOI超小口袋Si0.7Ge0.3无结隧道场效应管的表征","authors":"S. Tripathi, Shekhar Verma, Namrata Dhanda","doi":"10.1109/DEVIC.2019.8783891","DOIUrl":null,"url":null,"abstract":"The Tunnel FET has substantial potential to overcome limitations imposed due the scaling in low voltage region because of its steep subthreshold slope relative to its corresponding junction based MOSFET counterpart. Use of Si0.7Ge0.3 material as pocket region (0.5nm) enhances band-to-band tunneling by decreasing tunneling distance. The proposed pocket ultra small pocket Si0.7Ge0.3 Junction-less TFET(JLTFET) exploits advantage junction-less regions and p-type pocket region to improve device performance in subthreshold region showing improvement in subthreshold slope and better ON and OFF-state drain current ratio as compared to other similar TFET structures. Proposed ultra small pocket JLTFET shows high value $\\mathbf{I}_{\\mathbf{ON}}/\\mathbf{I}_{\\mathbf{OFF}}$ ratio and good subthreshold behaviour even with 2nm gate length and body thickness 0.5nm. All the designs proposed for n JLTFETs are designed on visual TCAD 2D/3D device simulator.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Characterisation of Ultra-Small Pocket Si0.7Ge0.3 Junction-less Tunnel FET with SOI\",\"authors\":\"S. Tripathi, Shekhar Verma, Namrata Dhanda\",\"doi\":\"10.1109/DEVIC.2019.8783891\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The Tunnel FET has substantial potential to overcome limitations imposed due the scaling in low voltage region because of its steep subthreshold slope relative to its corresponding junction based MOSFET counterpart. Use of Si0.7Ge0.3 material as pocket region (0.5nm) enhances band-to-band tunneling by decreasing tunneling distance. The proposed pocket ultra small pocket Si0.7Ge0.3 Junction-less TFET(JLTFET) exploits advantage junction-less regions and p-type pocket region to improve device performance in subthreshold region showing improvement in subthreshold slope and better ON and OFF-state drain current ratio as compared to other similar TFET structures. Proposed ultra small pocket JLTFET shows high value $\\\\mathbf{I}_{\\\\mathbf{ON}}/\\\\mathbf{I}_{\\\\mathbf{OFF}}$ ratio and good subthreshold behaviour even with 2nm gate length and body thickness 0.5nm. All the designs proposed for n JLTFETs are designed on visual TCAD 2D/3D device simulator.\",\"PeriodicalId\":294095,\"journal\":{\"name\":\"2019 Devices for Integrated Circuit (DevIC)\",\"volume\":\"50 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 Devices for Integrated Circuit (DevIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DEVIC.2019.8783891\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Devices for Integrated Circuit (DevIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DEVIC.2019.8783891","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Characterisation of Ultra-Small Pocket Si0.7Ge0.3 Junction-less Tunnel FET with SOI
The Tunnel FET has substantial potential to overcome limitations imposed due the scaling in low voltage region because of its steep subthreshold slope relative to its corresponding junction based MOSFET counterpart. Use of Si0.7Ge0.3 material as pocket region (0.5nm) enhances band-to-band tunneling by decreasing tunneling distance. The proposed pocket ultra small pocket Si0.7Ge0.3 Junction-less TFET(JLTFET) exploits advantage junction-less regions and p-type pocket region to improve device performance in subthreshold region showing improvement in subthreshold slope and better ON and OFF-state drain current ratio as compared to other similar TFET structures. Proposed ultra small pocket JLTFET shows high value $\mathbf{I}_{\mathbf{ON}}/\mathbf{I}_{\mathbf{OFF}}$ ratio and good subthreshold behaviour even with 2nm gate length and body thickness 0.5nm. All the designs proposed for n JLTFETs are designed on visual TCAD 2D/3D device simulator.
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