具有单周期调谐时间的回转速率控制输出驱动器

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI:10.1109/ASPDAC.2008.4484070

Young-Ho Kwak, I. Jung, Chulwoo Kim

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引用次数: 0

摘要

提出了一种开环数字方案的低功耗回转速率控制输出驱动器，锁紧时间为一个周期。建议的输出驱动器在使能时钟插入后的一个周期内保持在2.1 V/ns至3.6 V/ns的压转率。它采用0.18 um CMOS工艺实现，控制块在1gbps下消耗13.7 mW。

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A slew-rate controlled output driver with one-cycle tuning time

A low-power slew-rate controlled output driver with open loop digital scheme, one-cycle lock time is presented. Proposed output driver maintains slew rate in the range of 2.1 V/ns to 3.6 V/ns in a one cycle after the enable clock is inserted. It is implemented in 0.18 um CMOS process, and the control block consumes 13.7 mW at 1 Gbps.

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2008 Asia and South Pacific Design Automation Conference

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