一个基于反向的开源工具,用于处理器内核的后硅验证

Fabian Stuckmann, Pasha A. Fistanto, G. P. Vayá
{"title":"一个基于反向的开源工具,用于处理器内核的后硅验证","authors":"Fabian Stuckmann, Pasha A. Fistanto, G. P. Vayá","doi":"10.1109/MOCAST52088.2021.9493373","DOIUrl":null,"url":null,"abstract":"This paper presents an open-source tool, called PATARA, for post-silicon validation of Application-Specific Instruction set Processors (ASIP). PATARA is based on the REVERSI approach, which can significantly speed up the validation time of already fabricated chip designs. It enables the generation of automatic, randomized test-benches, which are then validated by the processor itself. PARATA extends the REVERSI approach by supporting subword parallalism (i.e., microSIMD hardware mechanism), multiple issue slots, and conditional execution. The configuration of PATARA is provided by XML files, which describe the instruction set architecture (ISA) of the target custom processor. Moreover, the modular structure of the PATARA tool enables the insertion of future features. The potential of this tool is shown in a case study, where part of the instruction set architecture of a VLIW-SIMD processor, called KAVUAKA, is verified. The results show that the use of the PATARA tool can achieve a higher code coverage than the previously used hand-written testbenches. It is worth mentioning that a high code coverage in pre-silicon verification generally implies a high coverage in post-silicon validation.","PeriodicalId":146990,"journal":{"name":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"PATARA: A REVERSI-Based Open-Source Tool for Post-Silicon Validation of Processor Cores\",\"authors\":\"Fabian Stuckmann, Pasha A. Fistanto, G. P. Vayá\",\"doi\":\"10.1109/MOCAST52088.2021.9493373\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an open-source tool, called PATARA, for post-silicon validation of Application-Specific Instruction set Processors (ASIP). PATARA is based on the REVERSI approach, which can significantly speed up the validation time of already fabricated chip designs. It enables the generation of automatic, randomized test-benches, which are then validated by the processor itself. PARATA extends the REVERSI approach by supporting subword parallalism (i.e., microSIMD hardware mechanism), multiple issue slots, and conditional execution. The configuration of PATARA is provided by XML files, which describe the instruction set architecture (ISA) of the target custom processor. Moreover, the modular structure of the PATARA tool enables the insertion of future features. The potential of this tool is shown in a case study, where part of the instruction set architecture of a VLIW-SIMD processor, called KAVUAKA, is verified. The results show that the use of the PATARA tool can achieve a higher code coverage than the previously used hand-written testbenches. It is worth mentioning that a high code coverage in pre-silicon verification generally implies a high coverage in post-silicon validation.\",\"PeriodicalId\":146990,\"journal\":{\"name\":\"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)\",\"volume\":\"47 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-07-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MOCAST52088.2021.9493373\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MOCAST52088.2021.9493373","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

本文提出了一个开源工具,称为PATARA,用于专用指令集处理器(ASIP)的硅后验证。PATARA基于REVERSI方法,可以显著加快已制造芯片设计的验证时间。它可以生成自动的、随机的测试台,然后由处理器本身进行验证。PARATA通过支持子字并行(即microSIMD硬件机制)、多问题槽和条件执行来扩展REVERSI方法。PATARA的配置由XML文件提供,XML文件描述了目标自定义处理器的指令集体系结构(ISA)。此外,PATARA工具的模块化结构可以插入未来的功能。该工具的潜力在一个案例研究中得到了展示,其中验证了VLIW-SIMD处理器(称为KAVUAKA)的部分指令集体系结构。结果表明,使用PATARA工具可以获得比以前使用的手工编写的测试平台更高的代码覆盖率。值得一提的是,硅前验证中的高代码覆盖率通常意味着硅后验证中的高覆盖率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
PATARA: A REVERSI-Based Open-Source Tool for Post-Silicon Validation of Processor Cores
This paper presents an open-source tool, called PATARA, for post-silicon validation of Application-Specific Instruction set Processors (ASIP). PATARA is based on the REVERSI approach, which can significantly speed up the validation time of already fabricated chip designs. It enables the generation of automatic, randomized test-benches, which are then validated by the processor itself. PARATA extends the REVERSI approach by supporting subword parallalism (i.e., microSIMD hardware mechanism), multiple issue slots, and conditional execution. The configuration of PATARA is provided by XML files, which describe the instruction set architecture (ISA) of the target custom processor. Moreover, the modular structure of the PATARA tool enables the insertion of future features. The potential of this tool is shown in a case study, where part of the instruction set architecture of a VLIW-SIMD processor, called KAVUAKA, is verified. The results show that the use of the PATARA tool can achieve a higher code coverage than the previously used hand-written testbenches. It is worth mentioning that a high code coverage in pre-silicon verification generally implies a high coverage in post-silicon validation.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信