S. A. A. Diaz, A. D. Sánchez, Luis Abraham Sánchez Gaspariano, Apolo Z. Escudero Uribe
{"title":"基于FPGA的4通道肌电特征提取","authors":"S. A. A. Diaz, A. D. Sánchez, Luis Abraham Sánchez Gaspariano, Apolo Z. Escudero Uribe","doi":"10.1109/CASME.2010.5706690","DOIUrl":null,"url":null,"abstract":"In this paper, an FPGA-based parallel architecture for the computation of myoelectric signal feature extraction, employing higher order statistics in presented. The three channels myoelectric signal is obtained directly from the user's muscles, in order to obtain prosthesis movement commands which emulate a biological elbow. The proposed architecture was realized in Very High Speed Integrated Circuit (BHSIC) by Hardware Description Language (VHDL), and functionally verified on a Xilinx board, which uses a Spartan-3 XC3S700AN FG48-4 FPGA. Experimental results are presented, and establish a maximum operation frequency of 44.570MHz.","PeriodicalId":337009,"journal":{"name":"2010 2nd Circuits and Systems for Medical and Environmental Applications Workshop (CASME)","volume":"132 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"4 channel signal based FPGA architecture for myolectric features extraction by H.O.S.\",\"authors\":\"S. A. A. Diaz, A. D. Sánchez, Luis Abraham Sánchez Gaspariano, Apolo Z. Escudero Uribe\",\"doi\":\"10.1109/CASME.2010.5706690\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, an FPGA-based parallel architecture for the computation of myoelectric signal feature extraction, employing higher order statistics in presented. The three channels myoelectric signal is obtained directly from the user's muscles, in order to obtain prosthesis movement commands which emulate a biological elbow. The proposed architecture was realized in Very High Speed Integrated Circuit (BHSIC) by Hardware Description Language (VHDL), and functionally verified on a Xilinx board, which uses a Spartan-3 XC3S700AN FG48-4 FPGA. Experimental results are presented, and establish a maximum operation frequency of 44.570MHz.\",\"PeriodicalId\":337009,\"journal\":{\"name\":\"2010 2nd Circuits and Systems for Medical and Environmental Applications Workshop (CASME)\",\"volume\":\"132 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 2nd Circuits and Systems for Medical and Environmental Applications Workshop (CASME)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CASME.2010.5706690\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 2nd Circuits and Systems for Medical and Environmental Applications Workshop (CASME)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CASME.2010.5706690","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
4 channel signal based FPGA architecture for myolectric features extraction by H.O.S.
In this paper, an FPGA-based parallel architecture for the computation of myoelectric signal feature extraction, employing higher order statistics in presented. The three channels myoelectric signal is obtained directly from the user's muscles, in order to obtain prosthesis movement commands which emulate a biological elbow. The proposed architecture was realized in Very High Speed Integrated Circuit (BHSIC) by Hardware Description Language (VHDL), and functionally verified on a Xilinx board, which uses a Spartan-3 XC3S700AN FG48-4 FPGA. Experimental results are presented, and establish a maximum operation frequency of 44.570MHz.