{"title":"快速可恢复异构四核锁步架构","authors":"Kai Liu, Yu Li, Ouyang Ling","doi":"10.1109/IEEECONF52377.2022.10013101","DOIUrl":null,"url":null,"abstract":"With the increasing demand of industry and automobile for reliability, various redundant software and hardware technologies are introduced into system design. In this paper, we present a fast recoverable heterogeneous quad-core lockstep architecture to mitigate single event upset (SEU) and common-mode failure(CMF) problems. Two ARM processors and Two RISC-V processors are integrated in a loosely-coupled lockstep mode and a recovery scheme is implemented without frequent processor context saving.","PeriodicalId":193681,"journal":{"name":"2021 International Conference on Advanced Computing and Endogenous Security","volume":"120 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Fast recoverable heterogeneous quad-core lockstep architecture\",\"authors\":\"Kai Liu, Yu Li, Ouyang Ling\",\"doi\":\"10.1109/IEEECONF52377.2022.10013101\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"With the increasing demand of industry and automobile for reliability, various redundant software and hardware technologies are introduced into system design. In this paper, we present a fast recoverable heterogeneous quad-core lockstep architecture to mitigate single event upset (SEU) and common-mode failure(CMF) problems. Two ARM processors and Two RISC-V processors are integrated in a loosely-coupled lockstep mode and a recovery scheme is implemented without frequent processor context saving.\",\"PeriodicalId\":193681,\"journal\":{\"name\":\"2021 International Conference on Advanced Computing and Endogenous Security\",\"volume\":\"120 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-04-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 International Conference on Advanced Computing and Endogenous Security\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEEECONF52377.2022.10013101\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 International Conference on Advanced Computing and Endogenous Security","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEEECONF52377.2022.10013101","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Fast recoverable heterogeneous quad-core lockstep architecture
With the increasing demand of industry and automobile for reliability, various redundant software and hardware technologies are introduced into system design. In this paper, we present a fast recoverable heterogeneous quad-core lockstep architecture to mitigate single event upset (SEU) and common-mode failure(CMF) problems. Two ARM processors and Two RISC-V processors are integrated in a loosely-coupled lockstep mode and a recovery scheme is implemented without frequent processor context saving.
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