K. Kawahara, Joe Sawada, Takumi Kamo, Y. Umeda, K. Takano
{"title":"用于DAC带宽三倍器的50 Gbps 49 mW CMOS模拟多路复用器","authors":"K. Kawahara, Joe Sawada, Takumi Kamo, Y. Umeda, K. Takano","doi":"10.1109/RWS53089.2022.9719979","DOIUrl":null,"url":null,"abstract":"This paper presents a CMOS analog multiplexer for a DAC bandwidth tripler. The bandwidth tripler extends the bandwidth of the DACs three times without generating image signals. We revealed the effect of the non-linearity of the AMUX in the bandwidth tripler, and pseudo differential switches were used to reduce the distortions. To compensate for the limited performance of CMOS devices, a broadband matching circuit was inserted into the output of the AMUX. Post-layout simulation results demonstrated a 50 Gbps PAM4 signal generation with a small power consumption of 49 mW. The power efficiency of the AMUX is only 0.98 pJ/bit, which is superior to the previous work.","PeriodicalId":113074,"journal":{"name":"2022 IEEE Radio and Wireless Symposium (RWS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 50 Gbps 49 mW CMOS Analog Multiplexer for a DAC Bandwidth Tripler\",\"authors\":\"K. Kawahara, Joe Sawada, Takumi Kamo, Y. Umeda, K. Takano\",\"doi\":\"10.1109/RWS53089.2022.9719979\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a CMOS analog multiplexer for a DAC bandwidth tripler. The bandwidth tripler extends the bandwidth of the DACs three times without generating image signals. We revealed the effect of the non-linearity of the AMUX in the bandwidth tripler, and pseudo differential switches were used to reduce the distortions. To compensate for the limited performance of CMOS devices, a broadband matching circuit was inserted into the output of the AMUX. Post-layout simulation results demonstrated a 50 Gbps PAM4 signal generation with a small power consumption of 49 mW. The power efficiency of the AMUX is only 0.98 pJ/bit, which is superior to the previous work.\",\"PeriodicalId\":113074,\"journal\":{\"name\":\"2022 IEEE Radio and Wireless Symposium (RWS)\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-01-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Radio and Wireless Symposium (RWS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RWS53089.2022.9719979\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Radio and Wireless Symposium (RWS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RWS53089.2022.9719979","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 50 Gbps 49 mW CMOS Analog Multiplexer for a DAC Bandwidth Tripler
This paper presents a CMOS analog multiplexer for a DAC bandwidth tripler. The bandwidth tripler extends the bandwidth of the DACs three times without generating image signals. We revealed the effect of the non-linearity of the AMUX in the bandwidth tripler, and pseudo differential switches were used to reduce the distortions. To compensate for the limited performance of CMOS devices, a broadband matching circuit was inserted into the output of the AMUX. Post-layout simulation results demonstrated a 50 Gbps PAM4 signal generation with a small power consumption of 49 mW. The power efficiency of the AMUX is only 0.98 pJ/bit, which is superior to the previous work.