Study on the Influence of Gate Parasitic Inductance on the SiC MOSFET Switching Performance

This paper presents a study on the influence of gate parasitic inductance on the SiC MOSFET switching performance. A switching transient equivalent circuit model that takes gate parasitic inductance into consideration is given to assess the SiC MOSFET switching characteristics. Then, the relationship between the voltage overshoot and the gate parasitic inductance is discussed, which can offer better insight into the switching performance when the gate parasitic inductance is varied. It is concluded that the local minimum of the voltage overshoot exists at a relatively large gate parasitic inductance. Furthermore, the analysis is substantiated by experimental results of the double pulse dynamic test platform. Based on this, the method for the gate drive to improve the switching performance of the SiC MOSFET is recommended.