Timing Window Shifting for Crosstalk Avoidance in 3D-IC

This paper presents an efficient heuristic algorithm for avoiding the occurrence of crosstalk affecting delay in 3D IC by downsizing or upsizing gates. The proposed algorithm classifies gate sizing into two steps, and to maximize the avoidance effect, downsizing in step1 and upsizing in step2 are applied sequentially to avoid aggressors adjacent to the critical path in turn. The proposed algorithm is tested on the benchmark circuit to verify its efficiency, and the experimental results show an average crosstalk avoidance effect of 9.45%. This result demonstrates the feasibility of the proposed new algorithm.