H. El Aabbaom, B. Gorissez, N. Rolland, A. Benlarbi-Delai, N. Fel, V. Allouche, P. Leclerc, B. Riondef, P. Rolland
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Design of a [DC - 20 GHz] buffered track and hold circuit in InP DHBT technology
This paper describes the design and realization of a buffered track and hoId (BTH) circuit fabricated in InP-InGaAs-InP double heterojunction bipolar transistor (DHBT) technology (FT = 180 GHz). This BTH is intended for a single shot, 20 GHz bandwidth and 40 GS/s sampling frequency digitizer based on the non simultaneous spatial sampling principle. Based on a high speed switched emitter follower (SEF), the BTH can ensure 20 GHz bandwidth signal compatible with the targeted objectives. First experimental results in the frequency domain and a novel optimized architecture leading to a combination between thr SEF arid the Cherry Hooper design based buffer are also presented.
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