2 mW 89 dB DR连续时间/spl Sigma//spl Delta/ ADC，增强了对宽带干扰的抗扰性

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332606

K. Philips, Peter Nuijten, R. Roovers, F. Muñoz, M. Tejero, A. Torralba

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引用次数: 19

摘要

提出了一种具有合并通道滤波器和可编程增益功能的连续时间/spl Sigma//spl Delta/ ADC。可以应用满量程以上的干扰，而不会影响弱所需信号的接收。合并后的设计在0.18 /spl μ m CMOS中占用0.14 mm/sup / /，功耗2 mW，在1mhz带宽下实现89 dB的动态范围(DR)。

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A 2 mW 89 dB DR continuous-time /spl Sigma//spl Delta/ ADC with increased immunity to wide-band interferers

A continuous-time /spl Sigma//spl Delta/ ADC with merged channel filter and programmable-gain functionality is presented. Interferers above full-scale can be applied without jeopardizing reception of weak desired signals. The merged design occupies 0.14 mm/sup 2/ in 0.18 /spl mu/m CMOS, consumes 2 mW, and achieves 89 dB of dynamic range (DR) in a 1 MHz bandwidth.

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2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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