低晶体管三元CNTFET SRAM单元的设计与性能评估

2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV) Pub Date : 2015-03-16 DOI:10.1109/EDCAV.2015.7060535

Pramod Srinivasan, Anirudha Bhat, Sneh Lata Murotiya, Anu Gupta

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引用次数: 10

摘要

碳纳米管场效应晶体管(CNTFET)由于具有更好的静电控制和高迁移率，已被证明是传统CMOS设计的一个有前途的替代品。提出了一种具有独立读写线的10晶体管三元存储单元的新设计。广泛的HSPICE仿真验证了该设计的读写功能。除了晶体管数量的显著减少，结果表明，与流行的存储单元设计相比，延迟至少减少了45%。

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Design and performance evaluation of a low transistor ternary CNTFET SRAM cell

Carbon Nanotube Field-Effect Transistor (CNTFET) has proved to be a promising alternative to conventional CMOS design owing to the better electrostatic control and high mobility. The paper presents a novel design of 10 Transistor ternary memory cell, with separate read and write lines. Extensive HSPICE simulations have validated the read-write functionality of the design. Besides a significant reduction in transistor count, results show at least 45% reduction in delay as compared to prevalent memory cell designs.

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2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV)

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