{"title":"基于奇偶校验的FPGA全局互连BIST方案的设计与实现","authors":"Xiaoling Sun, S. Xu, Jian Xu, P. Trouborst","doi":"10.1109/CCECE.2001.933621","DOIUrl":null,"url":null,"abstract":"This paper presents the design and implementation of a parity-based built-in self-test (BIST) scheme for interconnects of field programmable gate arrays (FPGAs). The self-test is achieved by using a set of proposed test configurations (TCs). Design flows were developed to enable the implementation. We utilized the existing features of FPGA design tools and developed a tool to automate the required interconnect routing. The conventional FPGA design flow was used to implement the BIST circuitry. A complete FPGA TC was presented. The pre- and post-mapping simulations were conducted. The results validate the feasibility of the proposed in-system testing scheme.","PeriodicalId":184523,"journal":{"name":"Canadian Conference on Electrical and Computer Engineering 2001. Conference Proceedings (Cat. No.01TH8555)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Design and implementation of a parity-based BIST scheme for FPGA global interconnects\",\"authors\":\"Xiaoling Sun, S. Xu, Jian Xu, P. Trouborst\",\"doi\":\"10.1109/CCECE.2001.933621\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design and implementation of a parity-based built-in self-test (BIST) scheme for interconnects of field programmable gate arrays (FPGAs). The self-test is achieved by using a set of proposed test configurations (TCs). Design flows were developed to enable the implementation. We utilized the existing features of FPGA design tools and developed a tool to automate the required interconnect routing. The conventional FPGA design flow was used to implement the BIST circuitry. A complete FPGA TC was presented. The pre- and post-mapping simulations were conducted. The results validate the feasibility of the proposed in-system testing scheme.\",\"PeriodicalId\":184523,\"journal\":{\"name\":\"Canadian Conference on Electrical and Computer Engineering 2001. Conference Proceedings (Cat. No.01TH8555)\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-05-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Canadian Conference on Electrical and Computer Engineering 2001. Conference Proceedings (Cat. No.01TH8555)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CCECE.2001.933621\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Canadian Conference on Electrical and Computer Engineering 2001. Conference Proceedings (Cat. No.01TH8555)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CCECE.2001.933621","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design and implementation of a parity-based BIST scheme for FPGA global interconnects
This paper presents the design and implementation of a parity-based built-in self-test (BIST) scheme for interconnects of field programmable gate arrays (FPGAs). The self-test is achieved by using a set of proposed test configurations (TCs). Design flows were developed to enable the implementation. We utilized the existing features of FPGA design tools and developed a tool to automate the required interconnect routing. The conventional FPGA design flow was used to implement the BIST circuitry. A complete FPGA TC was presented. The pre- and post-mapping simulations were conducted. The results validate the feasibility of the proposed in-system testing scheme.