Design Methodology Proposal of Digital Predistorter Using Matlab and Modelsim Cosimulation

This paper details the design of a Digital Predistorter (DPD) based on the Simplified Volterra Series (SVS) model. Our main contributions concern first the design of the predistorter unit using the Look Up Table (LUT) method without additional algorithms to decrease the high number of coefficients required for the PA model. Then, a Matlab and Modelsim cosimulation approach is discussed and performed to evaluate the proposed DPD architecture, in particular synthesis results are presented in terms of required Field Programmable Gate Array (FPGA) resources to implement the proposed predistorter. In addition, the performances of the proposed design are verified using a class AB GaN Power Amplifier (PA) driven by one carrier Long Term Evolution-Advanced (LTE-A) signal with 20 MHz channel bandwidth. It is proven that the LUT predistorter occupies only 55 % of the multipliers (DSP48E1) available in the Zynq-7000 FPGA. Also, the Adjacent Channel Power Ratio (ACPR) attains more than −45 dB.