{"title":"基于Matlab和Modelsim联合仿真的数字预失真器设计方法","authors":"H. Rezgui, F. Rouissi, A. Ghazel","doi":"10.1109/ICMCS.2018.8525972","DOIUrl":null,"url":null,"abstract":"This paper details the design of a Digital Predistorter (DPD) based on the Simplified Volterra Series (SVS) model. Our main contributions concern first the design of the predistorter unit using the Look Up Table (LUT) method without additional algorithms to decrease the high number of coefficients required for the PA model. Then, a Matlab and Modelsim cosimulation approach is discussed and performed to evaluate the proposed DPD architecture, in particular synthesis results are presented in terms of required Field Programmable Gate Array (FPGA) resources to implement the proposed predistorter. In addition, the performances of the proposed design are verified using a class AB GaN Power Amplifier (PA) driven by one carrier Long Term Evolution-Advanced (LTE-A) signal with 20 MHz channel bandwidth. It is proven that the LUT predistorter occupies only 55 % of the multipliers (DSP48E1) available in the Zynq-7000 FPGA. Also, the Adjacent Channel Power Ratio (ACPR) attains more than −45 dB.","PeriodicalId":272255,"journal":{"name":"2018 6th International Conference on Multimedia Computing and Systems (ICMCS)","volume":"197 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design Methodology Proposal of Digital Predistorter Using Matlab and Modelsim Cosimulation\",\"authors\":\"H. Rezgui, F. Rouissi, A. Ghazel\",\"doi\":\"10.1109/ICMCS.2018.8525972\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper details the design of a Digital Predistorter (DPD) based on the Simplified Volterra Series (SVS) model. Our main contributions concern first the design of the predistorter unit using the Look Up Table (LUT) method without additional algorithms to decrease the high number of coefficients required for the PA model. Then, a Matlab and Modelsim cosimulation approach is discussed and performed to evaluate the proposed DPD architecture, in particular synthesis results are presented in terms of required Field Programmable Gate Array (FPGA) resources to implement the proposed predistorter. In addition, the performances of the proposed design are verified using a class AB GaN Power Amplifier (PA) driven by one carrier Long Term Evolution-Advanced (LTE-A) signal with 20 MHz channel bandwidth. It is proven that the LUT predistorter occupies only 55 % of the multipliers (DSP48E1) available in the Zynq-7000 FPGA. Also, the Adjacent Channel Power Ratio (ACPR) attains more than −45 dB.\",\"PeriodicalId\":272255,\"journal\":{\"name\":\"2018 6th International Conference on Multimedia Computing and Systems (ICMCS)\",\"volume\":\"197 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 6th International Conference on Multimedia Computing and Systems (ICMCS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICMCS.2018.8525972\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 6th International Conference on Multimedia Computing and Systems (ICMCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMCS.2018.8525972","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
摘要
本文详细介绍了基于简化Volterra Series (SVS)模型的数字预失真器(DPD)的设计。我们的主要贡献首先涉及使用查找表(LUT)方法设计预失真器单元,而不需要额外的算法来减少PA模型所需的大量系数。然后,讨论并执行了Matlab和Modelsim联合仿真方法来评估所提出的DPD架构,特别是根据实现所提出的预失真器所需的现场可编程门阵列(FPGA)资源给出了综合结果。此外,采用20 MHz信道带宽的单载波LTE-A信号驱动的AB类GaN功率放大器(PA)验证了所提出设计的性能。事实证明,LUT预失真器仅占Zynq-7000 FPGA中可用乘法器(DSP48E1)的55%。相邻通道功率比(ACPR)达到−45 dB以上。
Design Methodology Proposal of Digital Predistorter Using Matlab and Modelsim Cosimulation
This paper details the design of a Digital Predistorter (DPD) based on the Simplified Volterra Series (SVS) model. Our main contributions concern first the design of the predistorter unit using the Look Up Table (LUT) method without additional algorithms to decrease the high number of coefficients required for the PA model. Then, a Matlab and Modelsim cosimulation approach is discussed and performed to evaluate the proposed DPD architecture, in particular synthesis results are presented in terms of required Field Programmable Gate Array (FPGA) resources to implement the proposed predistorter. In addition, the performances of the proposed design are verified using a class AB GaN Power Amplifier (PA) driven by one carrier Long Term Evolution-Advanced (LTE-A) signal with 20 MHz channel bandwidth. It is proven that the LUT predistorter occupies only 55 % of the multipliers (DSP48E1) available in the Zynq-7000 FPGA. Also, the Adjacent Channel Power Ratio (ACPR) attains more than −45 dB.