BIST环境下的可检测性评价

Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's Pub Date : 1991-04-15 DOI:10.1109/VTEST.1991.208170

Sheng Feng, Y. Malaiya

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引用次数: 0

摘要

内置自检(BIST)技术目前得到了广泛的应用。如何对其测试能力进行评估是一个重要的问题。BIST可检测性定义为被测电路故障集被检测的概率。这取决于测试点、待测电路以及作为数据压缩器的特征分析仪的特性。对特征分析的可检测性进行了评价。研究了随机和伪随机检测技术的BIST可检测性，并得出了一些结果。

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Evaluation of detectability in BIST environment

Built-in self-test (BIST) technique is now widely applied. How to estimate its testing capabilities is an important problem. BIST detectability is defined as the probability of that a fault set of the circuit-under-test is detected. It depends on the properties of the test at, circuit-under-test, as well as the signature analyser as a data compressor. The detectability of a signature analyzer is evaluated. The random and pseudorandom testing techniques are examined for their BIST detectability and several results are derived.<>

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Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's

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