A reconfigurable DCT/IDCT architecture for video codec: A Review

Among various transform techniques for image compression, the Discrete Cosine Transform (DCT) is the most popular and effective one in practical applications because it gives an almost optimal performance and can be implemented at an acceptable cost. The transform coding utilizing the Discrete Cosine Transform (DCT) has been commonly adopted in the various standards for image compression. These include the CCITT standard for video telephony, the JPEG (Joint Photographic Expert Group) standard for coloured still-image transmission and the MPEG (Motion Pictures Expert Group) standard for pictures on the storage media. MPEG was originally developed for digital television, its popularity and effectiveness as a storage/transmission format and abundance of content have made it attractive for use in personal video playback devices. DCT based coding schemes are also used for higher quality applications such as HDTV. Therefore, an architecture which rapidly computes DCT has become a key component of image compression VLSIs. This paper reviews the existing efficient algorithms for implementing the reconfigurable Discrete Cosine Transform (DCT)/ Inverse Discrete Cosine Transform (IDCT) architecture for multimedia applications and proposed an algorithm which offers high speed and reduced area. The proposed architecture uses an error compensated adder tree to perform shifting and addition operations. The reconfigurable architecture not only decreases the time of research and development but also saves fabrication cost. The advantages of the proposed architecture are that this architecture does not require multipliers and ROM. It only needs adders and shifters. In digital circuits, the area of the multipliers and ROM are larger than adders and shifters.