FPGA hardware architecture for stereoscopic image compression based on block matching, watermarking and hamming code

Image compression and size reduction increases the number of images stored on a memory space and reduces bandwidth consumption while increasing transmission speed on a communication channel. Images can be compressed and decompressed using different methods and algorithms. With the vast increase of quality and size, dedicated processors with parallel processing blocks such as FPGAs are mainly targeted to implementing faster processing circuits and algorithms. This paper proposes FPGA hardware architecture for a stereoscopic image compression algorithm based on block matching, watermarking and Hamming code.