阵列处理器的最佳容错设计方法

Proceedings of 1994 International Conference on Parallel and Distributed Systems Pub Date : 1994-12-19 DOI:10.1109/ICPADS.1994.590320

Chang Nian Zhang, T. M. Bachtiar, W. Chou

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引用次数: 2

摘要

提出了一种利用时空冗余设计容错收缩阵列的系统方法。该方法基于容错映射理论，将时空映射和并发错误检测技术相结合。通过这种设计方法，得到的收缩阵列具有容错性和最优性。此外，它还具有同时计算更多问题实例而无需额外成本的能力。

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An optimal fault-tolerant design approach for array processors

A systematic approach for designing fault tolerant systolic array using space/time redundancy is proposed. The approach is based upon a fault tolerant mapping theory which relates space-time mapping and concurrent error detection techniques. By this design approach, the resulting systolic array is fault tolerant and optimal. Besides, it has the capability to compute more problem instances simultaneously without extra cost.

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Proceedings of 1994 International Conference on Parallel and Distributed Systems

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